Parallel sorting algorithms have been proposed for VLSI implementation. Random defects in the silicon wafer and fabrication errors render processors in the wafer faulty, and may cause these algorithms to fail despite a significant number of nonfaulty processors. This paper presents twofault-tolerant pipelined sorting algorithms that would work on a wafer comprised of faulty and nonfaulty processors. Both the algorithms useO(n) processors and requireO(n) time to sortn elements.