This paper describes a verification technique that 1) enables a designer to verify properties of a partial design where some parts have not yet been completed, 2) yields a number of verification conditions growing linearly with the size of the design description. The technique was developed as part of work aimed at providing high-level tools for specification, verification, analysis, and synthesis of circuit descriptions written in a design language calledSynchronized Transitions [18]. The verification is supported by the mechanical theorem proverlp [5, 10].