VHDL-based verification methods require a formalized semantics of this hardware description language. As it has been shown recently that flowgraphs are an excellent means for defining the semantics of VHDL, we also use them to formalize full VHDL. However, our approach differs in important aspects from previous works. We use flowgraphs as an intermediate level for facilitating the deep embedding of VHDL in higher order logics, i.e. each VHDL program directly is a well-formed formula of the logic itself. This leads to a transparent semantic definition, since all constructs are defined explicitly as conservative extensions of the logic, and allows the direct reasoning about VHDL constructs. The relevant constructs of VHDL have been formalized, including delta delay. As we provide a general verification framework, different verification techniques such as model-checking, first-order theorem proving or invariant-based approaches may be used, depending on the verification task.