Quiescent current analysis and experimentation of defective CMOS circuits

descriptionPublicationkeyboard_double_arrow_right Article , Part of book or chapter of book 01 Jan 1992 Spain English Publisher:Springer Science and Business Media LLCJournal:Journal of Electronic Testing, volume 3, pages 337-348 (issn: 0923-8174, eissn: 1573-0727,

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Authors: Segura, J A; Champac, V H; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan; Rubio Sola, Jose Antonio;

doi: 10.1007/bf00135337 , 10.1007/978-1-4615-3146-3_5

handle: 2117/402335

Quiescent current analysis and experimentation of defective CMOS circuits

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Abstract

Physical defects widely encountered in today's CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. These models are used to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter. The results are compared with experimental data of integrated circuits fabricated with intentional defects. The influence of the characteristics of each defect on I DDQ has been investigated by electrical simulation and experimentation.

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Spain

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Keywords

Circuits electrònics--Proves, Electronic circuit design, Electronic circuits--Testing, Circuits electrònics--Disseny i construcció, Àrees temàtiques de la UPC::Enginyeria electrònica

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