In order to incorporate SER analysis into an industrial IC design flow, the algorithms must scale to industrial-sized circuits while maintaining accuracy. To address this challenge, we present AnSER, our linear-time method for logic-level soft-error analysis. AnSER achieves its low runtimes by means of functional simulation signatures, which enable a fast and accurate method for computing signal probability and observability, even in the presence of reconvergent fan-out. We analyze sequential circuits using AnSER along with multicycle simulation and time-frame expansion. We also show how to incorporate timing and electrical masking into the error probabilities predicted by this framework in order to more accurately model IC technology. We demonstrate results on IWLS and ISCAS benchmarks, which generally show 2-3 orders of magnitude speed-up over previous SER analyzers and high accuracy when validated against a state-of-the-art ATPG tool.