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Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism

descriptionPublicationkeyboard_double_arrow_right Part of book or chapter of book , Article 01 Jan 2004Publisher:Springer Berlin Heidelberg

Authors: Wolfgang Karl; André Seznec; Kemal Ebcioglu; Marco Aldinucci;

doi: 10.1007/978-3-540-27866-5_66

Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism

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Abstract

Parallel architecture design and ILP architectures are important topics at the core of every parallel system, affecting the total system performance in fundamental ways. Instruction-Level Parallelism has for decades represented a foremost performance booster of leading edge computing systems. The present topic, Euro-par Topic 8, includes parallel computer architectures, processor architecture (microarchitecture as well as compilation), the impact of emerging microprocessor architectures on parallel computer architectures, innovative memory designs to hide and reduce the access latency, multi-threading, and the impact of emerging applications on parallel computer architecture design.

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