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http://mediatum.ub.tum.de/doc/...
Part of book or chapter of book
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https://doi.org/10.1007/115569...
Part of book or chapter of book . 2005 . Peer-reviewed
Data sources: Crossref
DBLP
Conference object
Data sources: DBLP
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The Optimal Wire Order for Low Power CMOS

Authors: Paul Zuber; Peter Gritzmann; Michael Ritter; Walter Stechele;

The Optimal Wire Order for Low Power CMOS

Abstract

If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program. Due to their simplicity in implementation, both principles reported substantially differ from previous approaches. We also quantify the power optimization potential for wires based on a representative circuit model, with promising results.

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    influence
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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
2
Average
Average
Average