This paper presents the design of a new dynamic addition circuit based on a hybrid ripple-carry/carry-look-ahead/carry-bypass approach. In order to reduce power, the usage of duplicated carry-select stages is avoided. High computational speed is reached thanks to the implemented two-phase running. The latter makes the proposed adder able to exploit the time usually wasted for precharging dynamic circuits to accelerate the actual computation. Limited power dissipation and low area occupancy are guaranteed by optimizations done at both architecture and transistor levels. When realized using the UMC 0.18mm 1.8V CMOS technology, the new 64-bit adder exhibits a power-delay product of only 30.8pJ*ns and requires less than 3400 transistors.