In this work we studied the influence of the vector register size over two different concepts of vector architectures. Long vector registers play an important role in a conventional vector architecture, however, even using highly vectorisable codes, only a small fraction of that large vector registers is used. Reducing vector register size on a conventional vector architecture results in a severe performance degradation, providing slowdowns in the range of 1.8 to 3.8. When we included an out-of-order execution on a vector architecture, the need for long vector registers was reduced. We used a trace driven approach to simulate a selection of the Perfect Club and Specfp92 programs. The results of the simulations showed that the reduction of the register size on an out-of-order vector architecture led to slowdowns in the range of 1.04 to 1.9. These compare favourably with the values found for a conventional vector machine. Even when reducing the registers size to 1/4 of the original size on an out-of-order machine, the slowdown was between 1.04 and 1.5, and was better still than on a conventional vector machine. Finally, when comparing both architectures, using the same register file size (8kb) we found that the gains in performance using out-of-order execution were between 1.13 and 1.40.