ABSTRACT Balanced ternary digital logic circuits are designed based on memristors and applied to realize adder circuits, which can alleviate the Von Neumann architecture bottleneck and help extend Moore's Law. Four design methods are presented: decoder‐based method, multiplexer‐based method, method of combining multiplexers with single variable logic circuits, and method based on digital logic gates. The full‐adder circuits implemented by the above four distinct design methods are systematically compared and analyzed. This analysis highlights the strengths and limitations of each approach, thus providing a guideline for future development and optimization of balanced ternary combinational logic circuits aimed at achieving enhanced performance, power efficiency, and compactness.