SummaryIn this paper, the error‐correcting 4‐bit S‐boxes for cryptography applications with multiple error detection and correction are presented. Three 4‐bit S‐boxes which are used in the lightweight block ciphers PRESENT, Midori, and KLEIN are considered for implementation of the error‐correcting method. The proposed method does not require two redundant S‐boxes for repairing the S‐box. The main circuit of the S‐box is implemented concurrently with the low‐cost error‐correcting part of the structure. This reduces the overall area consumption and delay of the proposed error‐correcting method (the area consists of the 4‐bit S‐box and self‐checking/error‐correcting circuits). In the proposed error‐correcting method, the outputs of the S‐box are tested individually and it can detect and repair transient and permanent faults simultaneously. Therefore, the structure can detect and repair the single, double, triple, and quadruple faults at a time. The area and timing results, in 180 nm CMOS technology, show the proposed structures are acceptable in terms of area and delay overheads than those of the other methods.