Low‐voltage rail‐to‐rail switched buffer topologies

descriptionPublicationkeyboard_double_arrow_right Article 01 Jul 2001 Italy English Publisher:WileyJournal:International Journal of Circuit Theory and Applications, volume 29, pages 413-422 (issn: 0098-9886, eissn: 1097-007X,

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Authors: Giuseppe Ferri; Andrea Baschirotto;

doi: 10.1002/cta.160

handle: 11697/21807

Low‐voltage rail‐to‐rail switched buffer topologies

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Abstract

AbstractThis paper presents some CMOS rail‐to‐rail low‐voltage (1.2 V) switched buffer topologies, to be used as input stages in switched‐opamp circuits. The main buffer is based on the use of an op‐amp featuring rail‐to‐rail input and output swing with constant transconductance over the input common mode voltage. The designed buffer exhibits a total harmonic distortion of about ‐61 dB for 5 MHz clock frequency with 2 Vppinput amplitude. Its characteristics have been compared with those of other rail‐to‐rail switched buffers, based on the main CMOS OTA (simple, symmetrical, Miller), showing good distortion even at frequencies in the MHz range and satisfying the requirements for the series switches. Copyright © 2001 John Wiley & Sons, Ltd.

Country

Italy

Related Organizations

University of L'Aquila
Italy
University of Salento
Italy

Keywords

switched capacitors, Switching theory, application of Boolean algebra; Boolean functions, Applications of design theory to circuits and networks, low voltage, switched-opamp circuits, analogue design

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