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image/svg+xml Jakob Voss, based on art designer at PLoS, modified by Wikipedia users Nina and Beao Closed Access logo, derived from PLoS Open Access logo. This version with transparent background. http://commons.wikimedia.org/wiki/File:Closed_Access_logo_transparent.svg Jakob Voss, based on art designer at PLoS, modified by Wikipedia users Nina and Beao Concurrency and Comp...arrow_drop_down
image/svg+xml Jakob Voss, based on art designer at PLoS, modified by Wikipedia users Nina and Beao Closed Access logo, derived from PLoS Open Access logo. This version with transparent background. http://commons.wikimedia.org/wiki/File:Closed_Access_logo_transparent.svg Jakob Voss, based on art designer at PLoS, modified by Wikipedia users Nina and Beao
Concurrency and Computation Practice and Experience
Article . 2021 . Peer-reviewed
License: Wiley Online Library User Agreement
Data sources: Crossref
DBLP
Article . 2022
Data sources: DBLP
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A parallel hardware hypervisor for hardware‐accelerated cloud computing

Authors: Atakan Dogan; Kemal Ebcioglu;

A parallel hardware hypervisor for hardware‐accelerated cloud computing

Abstract

SummaryHardware‐accelerated cloud computing systems based on FPGA or ASIC chips have proved useful in providing power‐efficient acceleration for a variety of software applications. However, these computing systems rely on operating systems and hypervisors, which not only are implemented with inefficient software, but which also are incapable of handling massively parallel systems, due to the lack of parallelism and scalability in their algorithmic designs. As a result, power, performance, and scalability problems will emerge in an exascale cloud computing environment. As a solution to these problems, the present study proposes a parallel hardware hypervisor system implemented entirely in special‐purpose hardware without resorting to energy‐inefficient general‐purpose processors. Furthermore, the proposed hypervisor system virtualizes application‐specific multi‐chip supercomputers, in order to enable the virtual supercomputers to share available FPGA and semi‐configurable ASIC resources in a cloud system. Single‐chip verification studies based on Verilog simulation have been done to verify the functional correctness of the proposed hardware hypervisor system, which consumes only a fraction of hardware resources. This article will in particular focus on the virtualization of multi‐chip message‐passing based supercomputers using limited reconfigurable hardware resources.

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
3
Top 10%
Average
Average
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