AbstractCommunicating process architecture can be used to build efficient multicore chips scaling to hundreds of processors. Concurrent processing, communications and input–output are supported directly by the instruction set of the cores and by the protocol used in the on‐chip interconnect. Concurrent programs are compiled directly to the chip exploiting novel compiler optimizations. The architecture supports a variety of programming techniques, ranging from statically configured process networks to dynamic reconfiguration and mobile processes. Copyright © 2007 D. May.