This article presents a high-speed Booth multiplier using a redundant binary algorithm which replaces the final addition stage. The redundant binary algorithm converts redundant binary to natural binary in constant time to provide a faster result. The Xilinx ISE design software 14.1 is used for the synthesis of the proposed architecture and implementation is done on Virtex-4 vlx15sf363-12 device for comparison purpose. The proposed architecture proves to be almost 74% faster than Booth multiplier using carry propagate adder (CPA), almost 65% faster than Booth multiplier based on carrying-lookahead adder (CLA), and more than 50% faster than vedic squaring architectures present in literature.