BER (bit error rate) measurement is an important criterion to analyze digital communication systems. In literature this measurement generally performed through simulation programs like Matlab/Simulink. It is considered that the simulation programs may not represent a real communication system and also they are quite time consuming and expensive. However, modeling communication systems with parallel processing and fast modules such as FPGA (Field Programmable Gate Arrays) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) and performing BER measurements on this modules is much faster, closer to the reality. The main interest of this study is to demonstrate the performance of FPGA based models in communication systems and show their advantages and disadvantages compared to the simulator models. Despite the simple structure of FPGA it sometimes restricts a complete design of the system because of comprising only gates, logic operators, register etc. Simulator models such as the ones designed with Matlab have a huge library which provides flexibility in the design and analysis of the system. Software and hardware developers try to develop new ways such as HDL Coder and System Generator tools to get over these restrictions. But both methods still have some restrictions to design a better communication system. In this paper also this restrictions are investigated detailed. As an example, QPSK (Quadrature Phase Shift Keying) modulation is shown by using System Generator tool in this paper.