Along with progress in computers and network techniques, it is necessary to ensure that the transmission and storage of quantities of information be made more efficient. To solve this problem, many data compression techniques have been developed and applied in various fields. A speed-up of data processing is required in various systems that handle large quantities of information. However, it will be difficult to satisfy the requirement to speed up data compression by software or in a single CPU. Thus, it is desirable to create high-speed data compression/decompression hardware using VLSI/ULSI techniques. In this paper, the parallel architecture PAHL-C is proposed to implement an LZ77 coding algorithm, one of the most effective coding algorithms for various kinds of information. PAHL-C is designed to accelerate data compression. It improves the throughput of data compression by reducing redundancy in the search for the longest matching string of symbols, a task that requires most computation time in LZ77 coding. PAHL-C is designed in logic circuitry by using the PARTHENON high-level synthesis system and its performance is evaluated. We find that the throughput is about 20 or 25 MByte/s. Furthermore, the PAHL-D LZ77 decoding parallel architecture is proposed and its performance is evaluated. It is shown that PAHL-C and PAHL-D can be integrated into a PAHL system effectively. © 1998 Scripta Technica, Syst Comp Jpn, 29(8): 28–37, 1998