The applicability of discrete performance estimation methods to VLSI design
Copyright policy )The applicability of discrete performance estimation methods to VLSI design
Abstract Conditions necessary to produce correct asymptotic complexity results and realistic performance estimates for VLSI devices, using discrete high-level VLSI complexity models, are examined. A set of design constraints is formulated, based on results from two experiments involving suitably designed and fabricated VLSI devices. The basis of the complexity model is modified so that it satisfies the constraints. A case-study for an integer multiplier design shows that the modified model produces asymptotic results in agreement with empirical measurements. Low-level performance estimates are then obtained using the RC network delay model in conjunction with the VLSI complexity model.
- University of Leeds United Kingdom
specification of synchronous concurrent algorithms, Specification and verification (program logics, model checking, etc.), VLSI design, discret high-level VLSI complexity models, asymptotic complexity results, Circuits, networks, performance estimation, Performance evaluation, queueing, and scheduling in the context of computer systems
specification of synchronous concurrent algorithms, Specification and verification (program logics, model checking, etc.), VLSI design, discret high-level VLSI complexity models, asymptotic complexity results, Circuits, networks, performance estimation, Performance evaluation, queueing, and scheduling in the context of computer systems
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