Fully delay testable circuits obtained by covering ROBDD nodes with Invert-AND-OR sub-circuits and Invert-ANDXOR sub-circuits implementing Shannon decomposition formula are considered. Algorithms of finding test pairs for robust testable PDFs and validatable non robust testable PDFs of resulted circuits have been developed. Experimental results demonstrate essential simplification of suggested circuits in contrast to fully delay testable circuits obtained by covering each ROBDD node with only Invert-AND-XOR sub-circuit.