Abstract Lattice‐based cryptography is one of the most promising cryptographic scheme which lies on the hardness of ring‐learning‐with‐error (RLWE). A new variant of RLWE, known as binary‐ring‐learning‐with‐error (BRLWE), has less key size and more efficient hardware implementations compared to RLWE‐based schemes. The key arithmetic operation for BRLWE‐based encryption scheme is the implementation of arithmetic operation represented by , where both and are integer polynomials, and is a binary polynomial. An efficient architecture to perform the arithmetic operation over a polynomial ring is proposed. We employ two linear feedback shift register structures comprising ‐ net units in our design to reduce the computational time. This reduction in computational time yields to a significant improvement in the other performance metrics such as delay, area‐delay product (ADP), power‐delay product, throughput and efficiency compared to the existing designs. As per the experimental results, the authors’ proposed design has improvement in ADP when compared to the recently reported work.