Fully delay and multiple stuck-at fault testable sequential circuit design
Copyright policy )Fully delay and multiple stuck-at fault testable sequential circuit design
In this paper we show that it is possible to derive a sequential circuit either from a transition table or from a State Transition Graph (STG), so that the sequential circuit has the short test detecting all multiple stuck-at faults at gate poles of the circuit, and delay of each circuit path is detectable
- National Research University of Electronic Technology Russian Federation
конечные автоматы, монотонные функции, константные неисправности, КОНЕЧНЫЙ АВТОМАТ,ГРАФ ПЕРЕХОДОВ,НЕИСПРАВНОСТИ ЗАДЕРЖЕК ПУТЕЙ,КРАТНЫЕ КОНСТАНТНЫЕ НЕИСПРАВНОСТИ,МОНОТОННЫЕ ФУНКЦИИ,FINITE STATE MACHINE (FSM),STATE TRANSITION GRAPH (STG),PATH DELAY FAULTS (PDFS),MULTIPLE STUCK-AT FAULTS,MONOTONOUS FUNCTIONS, неисправности задержек путей
конечные автоматы, монотонные функции, константные неисправности, КОНЕЧНЫЙ АВТОМАТ,ГРАФ ПЕРЕХОДОВ,НЕИСПРАВНОСТИ ЗАДЕРЖЕК ПУТЕЙ,КРАТНЫЕ КОНСТАНТНЫЕ НЕИСПРАВНОСТИ,МОНОТОННЫЕ ФУНКЦИИ,FINITE STATE MACHINE (FSM),STATE TRANSITION GRAPH (STG),PATH DELAY FAULTS (PDFS),MULTIPLE STUCK-AT FAULTS,MONOTONOUS FUNCTIONS, неисправности задержек путей
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