In this paper a new context-based adaptive variable length coding (CAVLC) architecture proposed particularly aims to be implemented with Field Programmable Logics. The architecture is composed of a macro-pipeline formed by three stages. In the first stage, all coefficients are scanned and syntactic element “level” is encoded partially if needed. All the syntactic elements which had not been finished will be encoded in stage 2. At last, all the encoded syntactic elements will be assembled. The proposed design needs only 9 cycles to encode a 4×4 luma block in the worst case and is capable of processing 1080p@66.6 HDTV video streams coded in YCbCr 4:2:0, when it is implemented with a low-cost FPGA.