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Design and FPGA implementation of JAVA CARD coprocessor for EMV compatible IC bankcard

Authors: Di Wu; Liji Wu; Xiangmin Zhang;

Design and FPGA implementation of JAVA CARD coprocessor for EMV compatible IC bankcard

Abstract

To meet the urgent need of transferring magnetic stripe bankcard to IC bankcard, a 16-bit low power JAVA CARD coprocessor for EMV compatible IC bankcard is designed and implemented by FPGA. In order to speed up the running of the JAVA CARD applets, a novel 5-stage pipelined JAVA CARD coprocessor is achieved with pure logic circuits, which carries out the execution of 88 instructions out of 134 defined in the JAVA CARD Virtual Machine Specification 3.0 Classic Edition, while the remaining instructions are processed by the main 32-bit RISC processor. A pre-fetch instruction buffer and stack-top-register are used to ensure the fluency of the pipeline for accelerating the coprocessor. The design is verified to be feasible for the need of IC bankcard by FPGA and proved significantly faster than the regular software virtual machine, while remaining in a low power consumption level1.

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
0
Average
Average
Average
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