This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has only one self-checking sequential circuit, normal (unprotected) sequential circuit and not selftesting checker. It is proved the reliability properties of the suggested scheme both for single stuck-at faults (SAFs) at gate poles and path delay faults (PDFs), transient and intermittent. It is supposed that each next fault appears when a previous one has disappeared. Estimations of the schemes complexity are discussed.