This paper describes the basic principles of adaptive arithmetic coder, then analyzes the key modules of the coding process for VLSI realization and proposes good solutions, which especially include the time cost part implemented with parallel mechanism. With that, an optimized hardware model is built up, and the correctness is verified through Post-Place & Route model simulation. The synthesis result is also given to show the performance. At last, the experimental results show that our method is correct and efficient, it has theoretical significance and practical value.