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ACM Transactions on Embedded Computing Systems
Article . 2025 . Peer-reviewed
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https://dx.doi.org/10.48550/ar...
Article . 2025
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Cost-Effective Optimization and Implementation of the CRT-Paillier Decryption Algorithm for Enhanced Performance

Authors: Z.W. Huang; D. Deng; P.Y. Sun; G.F. Sun; X.M. Tang;

Cost-Effective Optimization and Implementation of the CRT-Paillier Decryption Algorithm for Enhanced Performance

Abstract

To address the information leak problem in cloud computing, privacy protection techniques are receiving widespread attention. Among them, the Paillier homomorphism algorithm is an effective one since it allows addition and scalar multiplication operations when information is in dencrypted state. However, its computational efficiency is limited by complex modulo operations due to the ciphertext expansion followed by encryption. To accelerate its decryption, the Chinese Remainder Theorem (CRT) is often used to optimize these modulo operations, which makes the decryption chain undesirably long in turn. To address this issue, we propose an eCRT-Paillier decryption algorithm that shortens the decryption computation chain by combining precomputed parameters and eliminating extra judgment operations introduced by Montgomery modular multiplications. These two improvements reduce 50% modular multiplications and 60% judgment operations in the postprocessing of the CRT-Paillier decryption algorithm. Based on these improvements, we propose a highly parallel full-pipeline architecture to remove stalls caused by multiplier reuse in traditional modular exponentiation operations. This architecture also adopts some optimization methods, such as simplifying modular exponentiation units by dividing the exponent into segments and parallelizing data flow by multi-core instantiation. Finally, a high-throughput and efficient Paillier accelerator named MESA is implemented on the Xilinx Virtex-7 FPGA for evaluation. As the experimental result shows, it can complete a decryption within 0.577ms under a 100 MHz clock when using a 2048-bit key. Compared with previous works in the identical conditions, MESA can achieve a 1.16 × to 313.21 × increase in throughput, as well as 2.59% to 96.04% improvement in the Area Time Product (ATP).

Keywords

Hardware Architecture, FOS: Computer and information sciences, Cryptography and Security, Hardware Architecture (cs.AR), Cryptography and Security (cs.CR)

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
0
Average
Average
Average
Green