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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing

Authors: Colleman, Steven; Shi, Man; Verhelst, Marian;

COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing

Abstract

To achieve high accuracy, convolutional neural networks (CNNs) are increasingly growing in complexity and diversity in layer types and topologies. This makes it very challenging to efficiently deploy such networks on custom processor architectures for resource-scarce edge devices. Existing mapping exploration frameworks enable searching for the optimal execution schedules or hardware mappings of individual network layers, by optimizing each layer's spatial (dataflow parallelization) and temporal unrolling (execution order). However, these tools fail to take into account the overhead of supporting different unrolling schemes within a common hardware architecture. Using a fixed unrolling scheme across all layers is also not ideal, as this misses significant opportunities for energy and latency savings from optimizing the mapping of diverse layer types. A balanced approach assesses the right amount of mapping flexibility needed across target neural networks, while taking into account the overhead to support multiple unrollings. This paper, therefore, presents COAC, a cross-layer design space exploration and mapping framework to optimize the flexibility of neural processing architectures by balancing configurability overhead against resulting energy and latency savings for end-to-end inference. COAC does not only provide a systematical analysis of the architectural overhead in function of the supported spatial unrollings, but also builds an automated flow to find the best unrolling combination(s) for efficient end-to-end inference with limited hardware overhead. Results demonstrate that architectures with carefully optimized flexibility can achieve up to 38% EDP (energy-delay-product) savings for a set of six neural networks at the expense of a relative area increase of 9.5%.

14 pages,17 figures.Journal IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Keywords

Optimization, data flow for reconfigurability, Technology, 1006 Computer Hardware, Science & Technology, Computer Hardware & Architecture, modeling of data reformatting, Convolutional neural network (CNN), Engineering, Electrical & Electronic, 0805 Distributed Computing, Systems and Control (eess.SY), Topology, Electrical Engineering and Systems Science - Systems and Control, Cross layer design, 0906 Electrical and Electronic Engineering, Engineering, Hardware, 4009 Electronics, sensors and digital hardware, Computer Science, FOS: Electrical engineering, electronic engineering, information engineering, Convolutional neural networks, Computer Science, Hardware & Architecture, Arrays, Neural networks, cross-layer

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
3
Top 10%
Average
Average
Green