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FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers

descriptionPublicationkeyboard_double_arrow_right Part of book or chapter of book , Article 01 Jan 2000Publisher:Springer Berlin Heidelberg
Authors: Bogdan Mătăsaru; Tudor Jebelean;

doi: 10.1007/3-540-44614-1_91

FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers

Abstract

We present the FPGA implementation of an extension of the binary plus-minus systolic algorithm which computes the GCD (greatest common divisor) and also the normal form of a rational number, without using division. A sample array for 8 bit operands consumes 83.4% of an Atmel 40K10 chip and operates at 25 MHz.

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
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