A high-speed residue-to-binary converter for three-moduli (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) RNS and a scheme for its VLSI implementation
Copyright policy )A high-speed residue-to-binary converter for three-moduli (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) RNS and a scheme for its VLSI implementation
Summary: A high-speed residue-to-binary converter for the moduli set \((2^k, 2^k- 1, 2^{k-1}- 1)\) is proposed. Compared to the previous converter based on this moduli set, the proposed one is 40\% faster. Also, the time-complexity product is improved by 20\%. Following the top-down very large scale integration design flow, the proposed converter is implemented in 0.5-micron CMOS technology. Based on this moduli set, layouts of the 8-, 16-, 32-, and 64-bit residue-to-binary converters, which can be used in further residual number system designs, are generated and simulation results obtained.
- The University of Texas at Dallas United States
- Concordia University Canada
Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), digital signal processing, VLSLI implementation, Mathematical problems of computer architecture
Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), digital signal processing, VLSLI implementation, Mathematical problems of computer architecture
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