FPGA based Optimized Decimator using Distributed Arithmetic Algorithm for Wireless Applications
FPGA based Optimized Decimator using Distributed Arithmetic Algorithm for Wireless Applications
In this paper, FPGA based enhanced decimator utilizing DA is introduced for remote applications for giving better answers for inspecting rate modifications. The proposed decimator is planned utilizing Poly stage disintegration strategy. Circulated Arithmetic (DA) Algorithm which is a multiplier free methodology is utilized for devouring less equipment assets and to bring about a rapid decimator. Equipment multifaceted nature is decreased by utilizing advanced Look up Table (LUT) apportioning. The proposed configuration shows an improvement of 6.2-14% in speed. By devouring practically same number of cuts and F/Flops, number of LUTs is diminished by 11.95-17.63% demonstrating prudent arrangement. At long last the created decimator configuration is mimicked and incorporated on Virtex 2 Pro based objective Field Programmable Gate Array (FPGA).
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