Presents a case study showing how a top-down structured generic parallel design method can be successfully applied to a typical multi-level computer vision algorithm. The case study involves a written postal address recognition system. The address verification is discussed in particular. Incrementally controllable speedups of up to 15 for the complete application were obtained using up to 29 processors. Although this speedup is insufficient to achieve the required real-time performance of processing 10 envelope images/second, it would be straightforward to apply the same parallel design model to current generation parallel processors such as the TMS320C40 or T9000 which have at least 10 times the processing power and communications bandwidth of the T800 transputers used as processing elements in the present case study. The range of algorithms utilised in the case study, and the flexibility of the parallel solutions generated, lead the authors to believe that the design method is applicable to a wide range of embedded vision applications.