In the world of big data there has been a steady shift from parallel to high speed serial digital communication buses which requires devices with much higher data throughput. Serializing the data and sending at a faster rate, reduces the pin counts which in turn lead to much smaller devices in an integrated circuit compared to parallel communication. Line coding can potentially help in high data transfers. In this paper 128b/130b line coding algorithm has been proposed which has the double the payload of conventional 64b/66b encoding technique, with same number of preamble bits. This increases the data transfer rate drastically. The polynomial for the scrambler has been used from IEEE clause. The proposed 128b/130b encoding algorithm has been coded using Verilog and simulated using Quartus II 9.0v .The parameters such as Setup time, Hold time, Maximum frequency, power and slack for 8b/10b, 64b/66b and 128b/130b has been compared and tabulated. The layout has been designed for 128b/130b using Cadence Encounter 14.26 tool. The comparison shows that proposed algorithm has higher data rate at the expense of increase in hardware utilization.