Multi-level per cell (MLC) /Triple-Level per cell (TLC) technique significantly improves storage density with low cost increases, which stores more than one bit per cell, but also drastically decreases reliability in NAND flash memory. As the bit number per cell increases, correspondingly cell-to-cell interference (CCI) becomes the major challenge for NAND flash memory technology scaling. Recently, low-density parity-check (LDPC) code is considered as the most appropriate scheme of next generation Error Correcting Code (ECC) in NAND flash memory. In this paper, by exploiting the intra-cell characteristics in TLC NAND flash memory channels, a low-complexity quantization and reliability-Aware iterative majority-logic decoding (QR-IMLGD) algorithm for LDPC code is proposed to reduce the memory read latency and effectively improve the throughput of LDPC decoding. The proposed algorithm takes advantage of highly unequal error probability of input log-likelihood-ratios (LLRs) in the same cells, employ small bit-level quantizer and update only less reliable variable nodes that are initiated with higher error probability LLR values. Simulation results show that the proposed QR-IMLGD algorithm can yield a noticeable improvement in decoding convergence rate without compromising the error performance in TLC NAND flash memory channels.