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Open Access Repository of IISc Research Publications
Conference object . 1997
Full-Text: http://eprints.iisc.ernet.in/6411/1/a_floating.pdf
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A floating-point validation suite for high-performance shared and distributed memory computing systems

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 22 Nov 2002 India Publisher:IEEE Comput. SocJournal:Proceedings Fourth International Conference on High-Performance Computing
Authors: Ghoshal, SK;

doi: 10.1109/hipc.1997.634476

A floating-point validation suite for high-performance shared and distributed memory computing systems

Abstract

A methodology to systematically identify and isolate bugs in floating point implementation in high performance multiple CPU computing systems is formulated. A validation suite is written and tested. Results show improper implementation. Proper implementation guidelines are suggested and prototyped.

Country
India
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Keywords

Supercomputer Education & Research Centre

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
1
Average
Average
Average
Green