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This study proposes a new low-complexity decoding algorithm for low-density parity check codes, which is a variation of the offset min-sum algorithm and achieves a similar performance with lower hardware cost. A finite precision study is presented and the hardware cost of the implementation of three very large scale integration architectures is evaluated. As a conclusion, the proposed algorithm achieves similar performance with an area saving of around 18, 10 and 14% for the memory-based partially parallel, fully parallel and sliced message passing implementations, respectively.
This research was supported by Fondo Europeo de Desarrollo Regional (FEDER), the Spanish Ministerio de Ciencia e Innovacion, under grant numbers TEC2008-06787 and TEC2011-27916.
TECNOLOGIA ELECTRONICA, Message passing, Decoding, TEORIA DE LA SEÑAL Y COMUNICACIONES, Parity check codes, LDPC CODES, VLSI
TECNOLOGIA ELECTRONICA, Message passing, Decoding, TEORIA DE LA SEÑAL Y COMUNICACIONES, Parity check codes, LDPC CODES, VLSI
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