
This paper introduces a method for scalable verification of cache coherence protocols described in the Promela language. Scalability means that resources spent on verification (first of all, machine time and memory) do not depend on the number of processors in the system under verification. The method is comprised of three main steps. First, a Promela model written for a certain configuration of the system is generalized to the model being parameterized with the number of processors. To do it, some assumptions on the protocol are used as well as simple induction rules. Second, the parameterized model is abstracted from the number of processors. It is done by syntactical transformations of the model assignments, expressions, and communication actions. Finally, the abstract model is verified with the Spin model checker in a usual way. The method description is accompanied by the proof of its correctness. It is stated that the suggested abstraction is conservative in a sense that every invariant (a property that is true in all reachable states) of the abstract model is an invariant of the original model (invariant properties are the properties of interest during verification of cache coherence protocols). The method has been automated by a tool prototype that, given a Promela model, parses the code, builds the abstract syntax tree, transforms it according to the rules, and maps it back to Promela. The tool (and the method in general) has been successfully applied to verification of the MOSI protocols implemented in the Elbrus computer systems.
Electronic computers. Computer science, MULTICORE MICROPROCESSORS,SHARED MEMORY MULTIPROCESSORS,CACHE COHERENCE PROTOCOLS,MODEL CHECKING,SPIN,PROMELA,МНОГОЯДЕРНЫЕ МИКРОПРОЦЕССОРЫ,МУЛЬТИПРОЦЕССОРЫ С РАЗДЕЛЯЕМОЙ ПАМЯТЬЮ,ПРОТОКОЛЫ КОГЕРЕНТНОСТИ ПАМЯТИ,ПРОВЕРКА МОДЕЛЕЙ, QA75.5-76.95, многоядерные микропроцессоры, мультипроцессоры с разделяемой памятью, протоколы когерентности памяти, проверка моделей, spin, promela
Electronic computers. Computer science, MULTICORE MICROPROCESSORS,SHARED MEMORY MULTIPROCESSORS,CACHE COHERENCE PROTOCOLS,MODEL CHECKING,SPIN,PROMELA,МНОГОЯДЕРНЫЕ МИКРОПРОЦЕССОРЫ,МУЛЬТИПРОЦЕССОРЫ С РАЗДЕЛЯЕМОЙ ПАМЯТЬЮ,ПРОТОКОЛЫ КОГЕРЕНТНОСТИ ПАМЯТИ,ПРОВЕРКА МОДЕЛЕЙ, QA75.5-76.95, многоядерные микропроцессоры, мультипроцессоры с разделяемой памятью, протоколы когерентности памяти, проверка моделей, spin, promela
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