In the modern era, DSP is widely used in electronics, notably in mobile technology. It uses LUT-based schemes (SOP) and uses arithmetic and logical operations to reach the sum of products. A method known as distributed arithmetic is used to speed up complex calculations involving the sum of products. Any DSPs processing speed can be increased by employing Distributed Arithmetic to speed up the ALU computations. Modern DSPs require Distributed Arithmetic and OBC High-Speed ALU to increase computation efficiency. It is the ALU that helps perform accurate computations on real-time signals. Proposed study a novel in-site method for designing a Distributed Arithmetic and Offset Binary Coding-based ALU core for High-Speed DSP Processors. Due to its inverse symmetry, the Offset Binary Coding approach can reduce the area in half. When designing diverse ALU structures, structural or hierarchical modeling is preferred. Several LUT-based distributed arithmetic decomposition's are constructed and compared. Xilinx 14.7 ISE will also be used for performing performance assessments in terms of area, speed, and power.