A post-layout design power optimization algorithm is suggested. Both, gate sizing andmulti threshold optimization methods are implemented. The main advantages are the improved performance characteristics and intactness of the initial design placement and routing. Free layout spaces due to decrease of optimized cell sizes is suggested to be filled withdecoupling capacitors which decreases powersupply noises. The algorithm ensures decreaseof static and dynamic power by respectably19% and 11% for eight-core OpenSPARC processor architectures. It demonstrates improvedoptimization time compared to existing algorithms by about 29%, in expense of decrease ofoptimized power by 2-5%