Multiplication is a fundamental arithmetic operation, central to the performance of arithmetic and logic units (ALUs) in nearly all electronic systems. As such, the design and optimization of multipliers play a crucial role in improving the efficiency of integrated circuits, particularly in applications involving digital signal processing, numerical computations, and embedded systems. With rapid advancements in semiconductor technology, there is an increasing demand for multiplier architectures that offer high speed, low power consumption, and minimal area usage. The complexity of a multiplier circuit is predominantly determined by the number of partial products and the efficiency of their reduction and summation. In modern Very-Large-Scale Integration (VLSI) design, optimizing the power, area, and speed trade-offs is critical to achieving high performance. To meet current design challenges, it is essential to adopt architectures that reduce delays and occupy minimal silicon area while consuming less power. Among various approaches, Parallel Prefix Adders (PPAs) have proven effective in reducing the carry propagation delay in adder trees, thereby accelerating multiplication operations. This study proposes a high-speed multiplier architecture utilizing a novel Parallel Prefix Tree (PPT) structure. The objective is to enhance computation speed while simultaneously reducing size and power consumption. The proposed design leverages the inherent advantages of prefix computation to optimize the performance of the final summation stage in the multiplier. Key performance parameters including logic delay, total delay, and memory usage will be evaluated and compared against existing multiplier architectures to validate the effectiveness of the proposed approach.