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https://doi.org/10.1109/hotchi...
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Scalable parallel programming

descriptionPublicationkeyboard_double_arrow_right Article 01 Aug 2008Publisher:IEEEJournal:2008 IEEE Hot Chips 20 Symposium (HCS)
Authors: John Nickolls; Ian Buck; Michael Garland; Kevin Skadron;

doi: 10.1109/hotchips.2008.7476525

Scalable parallel programming

Abstract

The advent of multicore CPUs and manycore GPUs means that mainstream processor chips are now parallel systems. Furthermore, their parallelism continues to scale with Moore's law. The challenge is to develop mainstream application software that transparently scales its parallelism to leverage the increasing number of processor cores, much as 3D graphics applications transparently scale their parallelism to manycore GPUs with widely varying numbers of cores.

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    popularity
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    influence
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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
63
Top 10%
Top 1%
Average