This paper proposes a Transform Coefficient Coding (TCC) architecture for High Efficiency Video Coding (HEVC) by using Selective Implementation Patterns. The architecture developed targets to exploit the benefits of tradeoffs between number of cycles and complexity depending upon the requirements, hence reducing the execution time. The input configuration to be sent in parallel, semi parallel and serial manner, efficiently implements the design. The so- called method of Pipelining is the key to selection of different pixel combinations of input video signal, allowing to give maximum flexibility to compute the integral part of TCC, the One Dimensional Discrete Cosine Transform (1D-DCT) and Two-Dimensional Discrete Cosine Transform (2D-DCT). Furthermore, with a slight modification, the same design can be used for computing Discrete Sine Transform (DST) as well. Coding in Verilog HDL and Implementation in Spartan 3 FPGA Kit enhances the adaptability of the proposed scheme. By evaluating the best available option, lowest hardware complexity, with 11 Look Up Tables (LUTs) and 7 registers, is achieved. The idea is to introduce selectivity and reuse in architecture in Video Coding technique so that the hardware cost and computational time can be reduced.