This paper describes the implementation on field programmable gate array (FPGA) of a turbo decoder for 3GPP Long-Term Evolution standard. Considering the high data rates required by this standard, parallel decoding architecture is used. The parallel decoding latency is reduced N times compared with the serial decoding latency, N being the parallelization factor, usually a power of 2. The decoding performances are similar for both serial and parallel schemes, when very low decoding latency is added to this theoretical parallel latency value. Taking advantage of the quadratic permutation polynomial interleaver properties, and considering some specific FPGA block memory characteristics, a novel simplified parallel decoding scheme is proposed, including only one interleaver, independently of the N value. Moreover, for the single interleaver, we propose a solution that exploits key arithmetic properties of the corresponding equation to perform the address computation in a recursive manner. The proposed method replaces divisions and multiplications by comparisons and subtractions. In addition, an even-odd merge sorting network provides correct data to all N decoding units.