A hardware-oriented block matching algorithm and its area-efficient VLSI implementation are presented. The proposed technique benefits from the simplicity of the Pixel Difference Classification algorithm (PDC) , further exploits the inherence of the characteristics of the data being processed, and the goal of an area-efficient implementation is reached. A quality investigation based on processing video sequences confirms the stability and performance of the proposed algorithm when compared with the conventional full-search as well as low-complexity techniques. Realized in TSMC 0.18-micron CMOS technology the chip has a core area of 1.01mm2. For a comparable video quality, the proposed implementation has shown a significant silicon area deduction compared with the recently published conventional implementations.