We present a method of integrating constrained sequence (CS) and error control (EC) codes for digital communication systems. This technique is based on multimode coding where a single source word (SW) is represented by a set of complementary EC code words (CWs). From this set the encoder selects the CW that best meets the CS goals of the system. These goals are to have balanced transmission and a high number of transitions to aid in clock recovery. The decoding structure avoids the problem of CS error propagation by performing error correction before decoding the CS code. A hardware implementation was constructed to verify code operation and to measure the power spectral density (PSD) which is shown to match calculations. The PSD plots show that the encoded sequence has a null at 0 Hz and thus it is dc-free. Furthermore, BER simulations demonstrate the superior performance of this combined EC and CS code on a dc-constrained noisy channel.