To address the challenges posed by propagation channel impairments and to meet the high data rate requirements of laser communications, this study introduces a pioneering low-density parity-check (LDPC) decoder characterized by its high throughput and low complexity. The unique design of this decoder, based on an inter-frame pipeline and intra-frame parallel (IFPP-IFP) scheme, is specifically tailored to maximize the efficiency of processing units, leading to a substantial increase in decoding throughput. The implementation of IFPP is realized through a novel full-overlap message passing (FOMP) scheme and a dynamic address access (DAA) algorithm, distinguishing it from current solutions. Additionally, the decoder employs a message packing strategy and low-complexity data alignment units to effectively achieve IFP. Compared to existing solutions, our hardware implementation on the Xilinx XCKU060 FPGA demonstrates significant progress. The decoder achieves a decoding throughput of 2.67 Gb/s at 10 iterations and 350MHz. Remarkably, when five decoders are used on a single FPGA device, the throughput soars to 13.3 Gb/s, outperforming state-of-the-art designs by 1.3 times and concurrently reducing resource consumption by half. This combination of resource efficiency and enhanced throughput highlights the innovative and superior nature of our proposed approach.