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Low power enhancements for parallel algorithms

Authors: S. Klauke; J. Gotze;

Low power enhancements for parallel algorithms

Abstract

In this paper we present a general approach for reducing switching activity on the algorithmic level. We concentrate on iterative algorithms that are suitable for an implementation on parallel processor arrays. The reduction is substantially reached by avoiding operations that hardly contribute to the convergence of the implemented algorithm. Our general approach is exemplified on the implementation of a specific algorithm, i.e. the eigenvalue decomposition (EVD) of a real symmetric matrix.

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selected citations
These citations are derived from selected sources.
This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Citations provided by BIP!
popularity
This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network.
BIP!Popularity provided by BIP!
influence
This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically).
BIP!Influence provided by BIP!
impulse
This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network.
BIP!Impulse provided by BIP!
2
Average
Average
Average
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