Cryptography is used for securing sensitive information from unauthorized access. A cryptochip needs to be tested so as to ensure its functionality. Scan based testing is the most popular technique employed for testing purposes, however, such testing of the cryptochips can lead to the retrieval of the secret information stored inside them by exploiting the scan chain structure known as the scan based side channel attack. Thus, it becomes crucial to guarantee the security of the cryptochip while maintaining its testing capabilities. In this paper, we have proposed two schemes to securely test the AES cryptochip by inserting a certain number of XOR gates and a combination of XOR gates and NOT gates at random positions inside the scan chain structure of the AES crypto module. Our results show that, without affecting the testability of the AES cryptochip, our proposed schemes are successfully able to guard itself against scan based side channel attacks with minimal area overhead of just 0.02% and with the probability of finding the scan chain structure being 1/2128.