Summary: Dedicated VLSI circuits, which provide a compact and fast implementation of artificial neural networks (ANNs), can release the full power of these structures. A mixed-mode analog/digital VLSI implementation of ANNs offers a tradeoff solution for speed, area, and flexibility. In this paper, a mixed-mode sampled-data (SD) implementation of ANNs is presented. A chip contains novel programmable switched-resistor (SR) synapses as well as a simple CMOS analog neuron is designed, fabricated, and tested. ANN model simulations are performed for a prototype multi- layer perceptron (MLP) model architecture which solves two-character recognition problems. The CMOS ANN circuit which implements the prototype MLP is tested using HSPICE simulations. An extended MLP model architecture is proposed to solve multi-character recognition problems. A parallelogram VLSI architecture is developed to implement the CMOS ANN circuit of the prototype MLP. A novel modular ANN chip which implements a two-character recognizer is designed using a \(1.2 \mu m\) CMOS technology. This paper demonstrates the feasibility of an SR CMOS VLSI implementation of ANNs for character recognition using the parallelogram developed VLSI architecture.