Dynamically Reconfigurable Hardware Architectures for Context-Based Statistical Compression of Visual and Data Content
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The purpose of this work is to investigate algorithms and hardware architectures for context-based statistical lossless compression of visual and data content using dynamically reconfigurable hardware to support optimal modelling strategies for each data and compression type. Entropy coding of the modelling output will be performed using a statically configured arithmetic coding engine. The current trend of network convergence where visual and data content are transmitted along the same physical channel suggests a technology capable of delivering optimal compression ratios and fast adaptation to the nature of the content will become increasingly important. These are the two key concepts that will drive this research effort. Context-based statistical compression differs fundamentally from dictionary-based compression as used in popular algorithms such as the ZIP family and it is recognised as being able to offer superior compression ratios to these. However, this has been only achieved with complex software algorithms that require considerable amounts of memory capacity and have very low throughputs in the range of thousands of CPU cycles per byte. This means that power-hungry Pentium 4 class microprocessors running at GHz rates are needed to provide the required computing power to run these advanced statistical algorithms and even these CPUs will find difficult to support applications such as telemedicine where still images, video and scientific data would require lossless real-time compression with high bandwidths. Other applications such as data, video and image transmission in space require the performance to be achieved in an energy and silicon efficient platform. To achieve the demands set by these applications we propose the first universal lossless compression hardware core combining context-based variable-order statistical modelling and arithmetic coding. At present, there are no practical hardware realisations of these techniques, since no satisfactory solutions have yet been proposed for a viable architecture.
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