The sustainable supply and efficient conversion of energy is of major concern in today’s societies and economies. In particular, this is valid for Switzerland and France due to increasing scarcity of mineable fossil energy sources, hosting different industrial entities in the energy, transportation and power electronics sector. Metal oxide semiconductor field-effect transistors (MOSFETs) are of key importance for e.g. decentralized electrical supply grids, electrical drive trains and electric cars, core businesses for ABB, EDF and STmicroelectronics companies. To date, such power devices are mainly realized on silicon. However, Silicon Carbide (4H-SiC) MOSFETs allow higher switching speeds, lower losses and simpler system topologies, thus enabling a reduction in overall system and material costs as well as higher efficiencies and reliabilities. This project aims at analyzing and innovating a critical process step in the fabrication of silicon carbide (SiC) based MOSFET, namely the creation of the SiO2/SiC interface crucial for a high conductance inversion channel. When comparing to state-of-the-art silicon technology, the channel mobility in SiC MOSFETs is very low and strongly dependent on the crystallographic direction. Therefore, in SiC MOSFETs, the inversion channel significantly contributes to the total on-resistance and thus device losses. SiC is commercially available only with surface being tilted 4 degrees with respect to the [0001] crystallographic basal plane. Since the thermal oxidation process is strongly orientation-dependent, the surface morphology of 4H-SiC is expected to signi?cantly in?uence the formation of the SiO2/SiC interface potentially leading to non-ideal oxidations and nonstoichiometric near-interface regions. Yet, the question of how the surface, and especially agglomerated macrosteps, affects the performance of Metal-Oxide-Semiconductor Field-E?ect Transistors (MOSFETs) is still largely unsolved. Main reason for this lack of knowledge is that the commercially available SiC epi-wafers (wafers with an epitaxial layer) used for MOSFET fabrication have irreproducible surface steps to allow for a proper characterization. In this project, we propose to overcome these limitations by using different annealing techniques to induce controlled modifications of the surface morphology to generate either regions without steps (on-axis mesas) or regions with periodically distributed large steps and terraces (>10nm and >200nm, respectively). With such modifications, we aim at studying the effects of the local crystal structure on thermal oxidations and ultimately understand their impact on channel characteristics of 4H-SiC MOSFETs and present strategies for improvements. This study will be both theoretical, using hybrid DFT-force fields and TCAD simulations, and experimental, inducing surface reconstructions and characterizing thermal oxides by means of MOS capacitors and MOSFETs in such reconstructed surfaces. A full understanding of the factors limiting the channel mobility at the SiC/SiO2 interface will allow to design manufacturing processes and MOSFET structures which outperform today’s devices by a factor of three or more in terms of on-resistance for 1.2kV 4H-SiC MOSFETs. This will substantially boost the power electronic systems efficiency. This project proposal is set for four years. A PhD student at the University of Lyon (LMI) will develop processes to modify the surface of SiC samples. A PhD working both at PSI and at ETH Zurich will fabricate and characterize MOS capacitors and MOSFETs on such reconstructed samples. We will use a patented patterning technique developed at PSI to analyze the SiO2/SiC interface of terraces and steps separately. Finally, a PhD student working at the University of Basel will develop a novel atomistic simulation code to theoretically understand the role of the steps on the oxidation process and their impact on the device behavior.